i3c: mipi-i3c-hci-pci: Define Multi-Bus instances for supported controllers

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Define Multi-Bus Instances at offset 0x400 for Intel controllers.

Intel SoCs include two I3C PCI devices in the Low Power Subsystem (LPSS),
each capable of hosting two I3C buses. Panther Lake and Wildcat Lake
support three buses in total (IDs 0–2), while Nova Lake supports four
(IDs 0–3).

Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260106164416.67074-12-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

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Adrian Hunter 2026-01-06 18:44:16 +02:00 • committed by Alexandre Belloni

parent 9b1679028e

commit 540a55a5ba

1 changed files with 22 additions and 13 deletions

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drivers/i3c/master/mipi-i3c-hci/mipi-i3c-hci-pci.c

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