KVM: x86: Add support for vICR APIC-write VM-Exits in x2APIC mode

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Upcoming Intel CPUs will support virtual x2APIC MSR writes to the vICR,
i.e. will trap and generate an APIC-write VM-Exit instead of intercepting
the WRMSR.  Add support for handling "nodecode" x2APIC writes, which
were previously impossible.

Note, x2APIC MSR writes are 64 bits wide.

Signed-off-by: Zeng Guang <guang.zeng@intel.com>
Message-Id: <20220419153516.11739-1-guang.zeng@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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Zeng Guang 2022-04-19 23:35:16 +08:00 • committed by Paolo Bonzini

parent 0b85baa5f4

commit 5413bcba7e

1 changed files with 21 additions and 3 deletions

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arch/x86/kvm/lapic.c

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