drm/msm/dpu: update UBWC config for sm8150 and sm8250

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Update the UBWC registers to the right values for sm8150 and sm8250.

This removes broken dpu_hw_reset_ubwc, which doesn't work because the
"force blk offset to zero to access beginning of register region" hack is
copied from downstream, where mapped region starts 0x1000 below what is
used in the upstream driver.

Also simplifies the overly complicated change that was introduced in
e4f9bbe9f8 to work around dpu_hw_reset_ubwc being broken.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>

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This commit is contained in:

Jonathan Marek 2020-07-10 20:47:25 -04:00 • committed by Rob Clark

parent de321dcc23

commit 544d8b9615

6 changed files with 42 additions and 90 deletions

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8

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

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8

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

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16

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

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18

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c

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7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h

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75

drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c

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