drm/amdgpu: use cached ih rb control reg offsets for vega10

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all the ih rb control register offsets are cached
at the beginning of ih_sw_init.

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Hawking Zhang 2020-12-01 23:13:12 +08:00 • committed by Alex Deucher

parent 21822b6a96

commit 554bdbf6de

1 changed files with 14 additions and 40 deletions

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drivers/gpu/drm/amd/amdgpu/vega10_ih.c

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