irqchip/gic-v3: Add workaround for Synquacer pre-ITS

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The Socionext Synquacer SoC's implementation of GICv3 has a so-called
'pre-ITS', which maps 32-bit writes targeted at a separate window of
size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device
ID taken from bits [device_id_bits + 1:2] of the window offset.
Writes that target GITS_TRANSLATER directly are reported as originating
from device ID #0.

So add a workaround for this. Given that this breaks isolation, clear
the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

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Ard Biesheuvel 2017-10-17 17:55:56 +01:00 • committed by Marc Zyngier

parent 9d111d4910

commit 558b01654d

3 changed files with 82 additions and 2 deletions

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4

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

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8

arch/arm64/Kconfig

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72

drivers/irqchip/irq-gic-v3-its.c

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