drm/radeon: fixes for gfx clockgating on SI

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Clockgating requires signalling between the CP and the
RLC to work properly.  Resetting the CP block in the
CP resume code messed up the internal coordination
between the blocks.  Removing the reset allows gfx
clockgating to work properly.  However, when gfx clock
gating is enabled, there is a strange interaction with
dpm which causes the chip to stay in the high performance
level all the time, so leave gfx clockgating disabled
for now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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This commit is contained in:

Alex Deucher 2013-08-15 16:20:26 -04:00

parent e16866ecfb

commit 5594a558fa

2 changed files with 9 additions and 18 deletions

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10

drivers/gpu/drm/radeon/radeon_asic.c

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17

drivers/gpu/drm/radeon/si.c

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