V4L/DVB (9937): cx18: Use a consistent crystal value for computing all PLL parameters

Browse source

Use a consistent crystal value of 28.636360 MHz for computing all PLL
parameters so clocks don't have relative error due to assumed crystal
value mismatches.  Also aimed to have all PLLs run their VOCs at close to
400 MHz to minimze the error of these PLLs as frequency synthesizers. Also
set the VDCLK and AIMCLK PLLs to sane values before the APU and CPU firmware
are loaded.  Also fixed I2S Master clock dividers.

Many thanks to Mike Bradley and Jeff Campbell for reporting this problem and
suggesting the solution, researching and experimenting, and performing
extensive testing to support their suggested solution.

Reported-by: Jeff Campbell <jac1dlists@gmail.com>
Reported-by: Mike Bradley <mike.bradley@incanetworks.com>
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

...

This commit is contained in:

Andy Walls 2008-12-20 23:48:57 -03:00 • committed by Mauro Carvalho Chehab

parent 57e24b629a

commit 55d81aa5c1

3 changed files with 191 additions and 45 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

165

drivers/media/video/cx18/cx18-av-audio.c

View file

2

drivers/media/video/cx18/cx18-av-core.c

View file

69

drivers/media/video/cx18/cx18-firmware.c

View file