scsi: ufs-mediatek: Fix unbalanced clock on/off

Browse source

MediaTek UFS clocks are separated to two parts and controlled by different
modules: ufs-mediatek and phy-ufs-mediatek.

If both Auto-Hibern8 and clk-gating feature are enabled, mphy power control
is not balanced thus unbalanced control also happens to the clocks probed
by phy-ufs-mediatek module.

Fix this issue by:

 - Promise usage of phy_power_on/off balanced

 - Remove phy_power_on/off control in suspend/resume vops since both can be
   handled in setup_clock vops only

Link: https://lore.kernel.org/r/20200601104646.15436-5-stanley.chu@mediatek.com
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

...

This commit is contained in:

Stanley Chu 2020-06-01 18:46:45 +08:00 • committed by Martin K. Petersen

parent 488edafb11

commit 561e3a8726

2 changed files with 38 additions and 23 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

60

drivers/scsi/ufs/ufs-mediatek.c

View file

1

drivers/scsi/ufs/ufs-mediatek.h

View file