clk: ingenic/jz4740: Fix "pll half" divider not read/written properly

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The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.

This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.

Restore the correct behaviour using the newly introduced .div_table
field.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20190701113606.4130-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

...

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Paul Cercueil 2019-07-01 13:36:06 +02:00 • committed by Stephen Boyd

parent 5f9e832c13

commit 568b9de48d

1 changed files with 8 additions and 1 deletions

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drivers/clk/ingenic/jz4740-cgu.c

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