drm/i915: Include display_mmio_offset in sequencer index/data registers

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SR01 needs to be touched to disable VGA on non-UMS setups too.
So the sequencer registers need to include the appripriate offset
on VLV.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2013-01-25 21:44:45 +02:00 • committed by Daniel Vetter

parent 67cfc2032b

commit 56a12a5092

1 changed files with 8 additions and 2 deletions

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drivers/gpu/drm/i915/i915_reg.h

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