clk: tegra: pll: Change misc_reg count from 3 to 6

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New SoC's may have more than 3 MISC registers, so bump up the array size
and use a #define to be more informative about the value.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Bill Huang 2015-06-18 17:28:22 -04:00 • committed by Thierry Reding

parent 204c85d124

commit 56fd27b31f

1 changed files with 3 additions and 1 deletions

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drivers/clk/tegra/clk.h

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