drm/amd/display: fix code to control 48mhz refclk

Browse source

[Why]
The SMU message to enable this feature looks at argument. Previous code
didn't send right argument. This change will allow the feature to be
be enabled.

[How]
Fixed one issue where SMU message to enable the feature was sent without
setting the parameter.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Eric Yang 2019-07-18 13:56:59 -04:00 • committed by Alex Deucher

parent ab4a4072f2

commit 57133a28bc

4 changed files with 8 additions and 7 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

7

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

View file

4

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

View file

2

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h

View file

2

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

View file