iio: Aspeed ADC

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Aspeed BMC SoCs include a 16 channel, 10-bit ADC. Low and high threshold
interrupts are supported by the hardware but are not currently implemented.

Signed-off-by: Rick Altherr <raltherr@google.com>
Tested-by: Xo Wang <xow@google.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>

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Rick Altherr 2017-03-28 14:52:59 -07:00 • committed by Jonathan Cameron

parent fb87ecf19e

commit 573803234e

3 changed files with 307 additions and 0 deletions

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11

drivers/iio/adc/Kconfig

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1

drivers/iio/adc/Makefile

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295

drivers/iio/adc/aspeed_adc.c

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