drm/i915/adlp: Add workaround to disable CMTG clock gating

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The driver doesn't depend atm on the common mode timing generator
functionality (it would be used for some power saving feature and panel
timing synchronization), however DMC will corrupt the CMTG registers
across DC5 entry/exit sequences unless the CMTG clock gating is
disabled. This in turn can lead to at least the DPLL0/1 configuration
getting stuck at their last state, which means we can't reprogram them
to a new config.

Add the corresponding Bspec workaround to prevent the above.

v2: Fix checkpatch errors. (CI, Jose)

Cc: Uma Shankar <uma.shankar@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210727134400.101290-1-imre.deak@intel.com

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This commit is contained in:

Imre Deak 2021-07-27 16:44:00 +03:00

parent ba3b049f47

commit 573d7ce4f6

2 changed files with 21 additions and 0 deletions

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18

drivers/gpu/drm/i915/display/intel_display.c

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3

drivers/gpu/drm/i915/i915_reg.h

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