clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks

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To support VOU VGA display driver with different modes, we need to set
flag for a few clocks, so that clk_set_rate() call in VOU driver can get
VGA device desired pixel rate.

While at it, the divider between pll_vga and clk_vga gets corrected, as
it's 1:1 instead of 1:2.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Jun Nie <jun.nie@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>

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Shawn Guo 2017-03-21 16:38:21 +08:00 • committed by Michael Turquette

parent cf091ee994

commit 5790d80176

1 changed files with 3 additions and 3 deletions

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drivers/clk/zte/clk-zx296718.c

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