MIPS: Ingenic: Fix bugs when detecting X1000's L2 cache.

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1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: ralf@linux-mips.org
Cc: paul@crapouillou.net
Cc: jhogan@kernel.org
Cc: malat@debian.org
Cc: gregkh@linuxfoundation.org
Cc: tglx@linutronix.de
Cc: allison@lohutok.net
Cc: syq@debian.org
Cc: chenhc@lemote.com
Cc: jiaxun.yang@flygoat.com

...

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Zhou Yanjie 2019-08-02 16:27:36 +08:00 • committed by Paul Burton

parent dc7077f89a

commit 579de8f86b

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1 changed files with 20 additions and 7 deletions

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arch/mips/mm/sc-mips.c

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