ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll

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The fout clock of BPLL and MPLL have a selectable source on EXYNOS5250.
The clock options are a fixed divided by 2 clock and the output of the
PLL itself. Add support for these new clock instances.

Signed-off-by: Kisoo Yu <ksoo.yu@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
[kgene.kim@samsung.com: moved common pll stuff into s5p-clock.c]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

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Kisoo Yu 2012-04-24 14:54:15 -07:00 • committed by Kukjin Kim

parent f10590c983

commit 57b317f912

4 changed files with 80 additions and 2 deletions

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46

arch/arm/mach-exynos/clock-exynos5.c

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2

arch/arm/mach-exynos/include/mach/regs-clock.h

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4

arch/arm/plat-samsung/include/plat/s5p-clock.h

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30

arch/arm/plat-samsung/s5p-clock.c

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