phy: qcom: qmp-pcie: register second optional PHY AUX clock

Browse source

The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock,
add the code to register it for PHYs configs that sets a aux_clock_rate.

In order to get the right clock, add qmp_pcie_clk_hw_get() which uses
the newly introduced QMP_PCIE_PIPE_CLK & QMP_PCIE_PHY_AUX_CLK clock
IDs and also supports the legacy bindings by returning the PIPE clock
when #clock-cells=0.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-3-3ec0a966d52f@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

...

This commit is contained in:

Neil Armstrong 2024-03-22 10:42:40 +01:00 • committed by Vinod Koul

parent 677b45114b

commit 583ca9ccfa

1 changed files with 75 additions and 3 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

78

drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

View file