clk: rockchip: rk3576: fix source muxes for SPI0..SPI4

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The TRM defines available source muxes for SPI0..SPI4 as
 - b00: clk_gpll_div6_src
 - b01: clk_gpll_div8_src
 - b10: clk_cpll_div10_src
 - b11: clk_xin_osc0_func

Which doesn't match what the current clock driver implements, making it
impossible to derive some SPI clock rates such as 37.125 MHz (which
requires clk_gpll_div8_src as the source mux).

Add a correct mux definition per TRM and point SPI0..SPI4 clocks at it.

Fixes: cc40f5baa9 ("clk: rockchip: Add clock controller for the RK3576")
Signed-off-by: Alexey Charkov <alchark@flipper.net>
Link: https://patch.msgid.link/20260805-rk3576-spi-clk-v1-1-2f040d0d163b@flipper.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

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This commit is contained in:

Alexey Charkov 2026-08-05 17:45:09 +04:00 • committed by Heiko Stuebner

parent b520d056f2

commit 586ff159ec

1 changed files with 6 additions and 5 deletions

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drivers/clk/rockchip/clk-rk3576.c

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