clk: qcom: clk-rcg2: Update logic to calculate D value for RCG

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The display pixel clock has a requirement on certain newer platforms to
support M/N as (2/3) and the final D value calculated results in
underflow errors.
As the current implementation does not check for D value is within
the accepted range for a given M & N value. Update the logic to
calculate the final D value based on the range.

Fixes: 99cbd064b0 ("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@codeaurora.org

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Taniya Das 2022-02-27 23:25:35 +05:30 • committed by Bjorn Andersson

parent 89f0f1a460

commit 58922910ad

1 changed files with 11 additions and 2 deletions

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drivers/clk/qcom/clk-rcg2.c

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