clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment

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PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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Geert Uytterhoeven 2018-09-18 10:55:29 +02:00

parent 7c0043c0a4

commit 5915838b7a

1 changed files with 2 additions and 2 deletions

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drivers/clk/renesas/r8a77990-cpg-mssr.c

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