diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 511c9dd3778d..f444207fa550 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -316,18 +316,6 @@ static void cik_sdma_gfx_stop(struct amdgpu_device *adev) } } -/** - * cik_sdma_rlc_stop - stop the compute async dma engines - * - * @adev: amdgpu_device pointer - * - * Stop the compute async dma queues (CIK). - */ -static void cik_sdma_rlc_stop(struct amdgpu_device *adev) -{ - /* XXX todo */ -} - /** * cik_ctx_switch_enable - stop the async dma engines context switch * @@ -400,7 +388,6 @@ static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) if (!enable) { cik_sdma_gfx_stop(adev); - cik_sdma_rlc_stop(adev); } for (i = 0; i < adev->sdma.num_instances; i++) { @@ -501,20 +488,6 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev) return 0; } -/** - * cik_sdma_rlc_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * - * Set up the compute DMA queues and enable them (CIK). - * Returns 0 for success, error for failure. - */ -static int cik_sdma_rlc_resume(struct amdgpu_device *adev) -{ - /* XXX todo */ - return 0; -} - /** * cik_sdma_load_microcode - load the sDMA ME ucode * @@ -577,9 +550,6 @@ static int cik_sdma_start(struct amdgpu_device *adev) /* start the gfx rings and rlc compute queues */ r = cik_sdma_gfx_resume(adev); - if (r) - return r; - r = cik_sdma_rlc_resume(adev); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 657ef6c93c61..7c8acdf73d44 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -349,18 +349,6 @@ static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) } } -/** - * sdma_v2_4_rlc_stop - stop the compute async dma engines - * - * @adev: amdgpu_device pointer - * - * Stop the compute async dma queues (VI). - */ -static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev) -{ - /* XXX todo */ -} - /** * sdma_v2_4_enable - stop the async dma engines * @@ -376,7 +364,6 @@ static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) if (!enable) { sdma_v2_4_gfx_stop(adev); - sdma_v2_4_rlc_stop(adev); } for (i = 0; i < adev->sdma.num_instances; i++) { @@ -477,20 +464,6 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) return 0; } -/** - * sdma_v2_4_rlc_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * - * Set up the compute DMA queues and enable them (VI). - * Returns 0 for success, error for failure. - */ -static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev) -{ - /* XXX todo */ - return 0; -} - /** * sdma_v2_4_start - setup and start the async dma engines @@ -509,9 +482,6 @@ static int sdma_v2_4_start(struct amdgpu_device *adev) /* start the gfx rings and rlc compute queues */ r = sdma_v2_4_gfx_resume(adev); - if (r) - return r; - r = sdma_v2_4_rlc_resume(adev); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 63c94fe52b3c..e929d62721b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -526,18 +526,6 @@ static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) } } -/** - * sdma_v3_0_rlc_stop - stop the compute async dma engines - * - * @adev: amdgpu_device pointer - * - * Stop the compute async dma queues (VI). - */ -static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) -{ - /* XXX todo */ -} - /** * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch * @@ -614,7 +602,6 @@ static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) if (!enable) { sdma_v3_0_gfx_stop(adev); - sdma_v3_0_rlc_stop(adev); } for (i = 0; i < adev->sdma.num_instances; i++) { @@ -752,20 +739,6 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) return 0; } -/** - * sdma_v3_0_rlc_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * - * Set up the compute DMA queues and enable them (VI). - * Returns 0 for success, error for failure. - */ -static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) -{ - /* XXX todo */ - return 0; -} - /** * sdma_v3_0_start - setup and start the async dma engines * @@ -784,9 +757,6 @@ static int sdma_v3_0_start(struct amdgpu_device *adev) /* start the gfx rings and rlc compute queues */ r = sdma_v3_0_gfx_resume(adev); - if (r) - return r; - r = sdma_v3_0_rlc_resume(adev); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index ded1f8abfb08..bdd140887e10 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -933,18 +933,6 @@ static void sdma_v4_0_gfx_enable(struct amdgpu_device *adev, bool enable) } } -/** - * sdma_v4_0_rlc_stop - stop the compute async dma engines - * - * @adev: amdgpu_device pointer - * - * Stop the compute async dma queues (VEGA10). - */ -static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) -{ - /* XXX todo */ -} - /** * sdma_v4_0_page_stop - stop the page async dma engines * @@ -1047,7 +1035,6 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) if (!enable) { sdma_v4_0_gfx_enable(adev, enable); - sdma_v4_0_rlc_stop(adev); if (adev->sdma.has_page_queue) sdma_v4_0_page_stop(adev); } @@ -1312,21 +1299,6 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev) } } -/** - * sdma_v4_0_rlc_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * - * Set up the compute DMA queues and enable them (VEGA10). - * Returns 0 for success, error for failure. - */ -static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) -{ - sdma_v4_0_init_pg(adev); - - return 0; -} - /** * sdma_v4_0_load_microcode - load the sDMA ME ucode * @@ -1426,9 +1398,7 @@ static int sdma_v4_0_start(struct amdgpu_device *adev) sdma_v4_0_ctx_switch_enable(adev, true); sdma_v4_0_enable(adev, true); } else { - r = sdma_v4_0_rlc_resume(adev); - if (r) - return r; + sdma_v4_0_init_pg(adev); } for (i = 0; i < adev->sdma.num_instances; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 5212ea6c46a2..7e8d528cf422 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -520,20 +520,6 @@ static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, } } -/** - * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines - * - * @adev: amdgpu_device pointer - * @inst_mask: mask of dma engine instances to be disabled - * - * Stop the compute async dma queues. - */ -static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, - uint32_t inst_mask) -{ - /* XXX todo */ -} - /** * sdma_v4_4_2_inst_page_stop - stop the page async dma engines * @@ -632,7 +618,6 @@ static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, if (!enable) { sdma_v4_4_2_inst_gfx_stop(adev, inst_mask); - sdma_v4_4_2_inst_rlc_stop(adev, inst_mask); if (adev->sdma.has_page_queue) sdma_v4_4_2_inst_page_stop(adev, inst_mask); @@ -888,23 +873,6 @@ static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev) } -/** - * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * @inst_mask: mask of dma engine instances to be enabled - * - * Set up the compute DMA queues and enable them. - * Returns 0 for success, error for failure. - */ -static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, - uint32_t inst_mask) -{ - sdma_v4_4_2_init_pg(adev); - - return 0; -} - /** * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode * @@ -1019,9 +987,7 @@ static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask); sdma_v4_4_2_inst_enable(adev, true, inst_mask); } else { - r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask); - if (r) - return r; + sdma_v4_4_2_init_pg(adev); } tmp_mask = inst_mask; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index a6fcef36c501..d24659a69382 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -574,18 +574,6 @@ static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask) } } -/** - * sdma_v5_0_rlc_stop - stop the compute async dma engines - * - * @adev: amdgpu_device pointer - * - * Stop the compute async dma queues (NAVI10). - */ -static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) -{ - /* XXX todo */ -} - /** * sdma_v5_0_ctx_switch_enable - stop the async dma engines context switch * @@ -661,7 +649,6 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); if (!enable) { sdma_v5_0_gfx_stop(adev, 1 << inst_mask); - sdma_v5_0_rlc_stop(adev); } if (amdgpu_sriov_vf(adev)) @@ -858,19 +845,6 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) return 0; } -/** - * sdma_v5_0_rlc_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * - * Set up the compute DMA queues and enable them (NAVI10). - * Returns 0 for success, error for failure. - */ -static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) -{ - return 0; -} - /** * sdma_v5_0_load_microcode - load the sDMA ME ucode * @@ -951,7 +925,6 @@ static int sdma_v5_0_start(struct amdgpu_device *adev) r = sdma_v5_0_gfx_resume(adev); if (r) return r; - r = sdma_v5_0_rlc_resume(adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 35cdf6c149f8..76e1f9f39525 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -424,18 +424,6 @@ static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask) } } -/** - * sdma_v5_2_rlc_stop - stop the compute async dma engines - * - * @adev: amdgpu_device pointer - * - * Stop the compute async dma queues. - */ -static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev) -{ - /* XXX todo */ -} - /** * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch * @@ -510,7 +498,6 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); if (!enable) { sdma_v5_2_gfx_stop(adev, inst_mask); - sdma_v5_2_rlc_stop(adev); } if (!amdgpu_sriov_vf(adev)) { @@ -705,19 +692,6 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) return 0; } -/** - * sdma_v5_2_rlc_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * - * Set up the compute DMA queues and enable them. - * Returns 0 for success, error for failure. - */ -static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev) -{ - return 0; -} - /** * sdma_v5_2_load_microcode - load the sDMA ME ucode * @@ -851,7 +825,6 @@ static int sdma_v5_2_start(struct amdgpu_device *adev) r = sdma_v5_2_gfx_resume(adev); if (r) return r; - r = sdma_v5_2_rlc_resume(adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 0b64eb5b32e9..d9e134b2bc48 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -407,18 +407,6 @@ static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev) } } -/** - * sdma_v6_0_rlc_stop - stop the compute async dma engines - * - * @adev: amdgpu_device pointer - * - * Stop the compute async dma queues. - */ -static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev) -{ - /* XXX todo */ -} - /** * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts * @@ -457,7 +445,6 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) if (!enable) { sdma_v6_0_gfx_stop(adev); - sdma_v6_0_rlc_stop(adev); } if (amdgpu_sriov_vf(adev)) @@ -642,19 +629,6 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) return 0; } -/** - * sdma_v6_0_rlc_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * - * Set up the compute DMA queues and enable them. - * Returns 0 for success, error for failure. - */ -static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev) -{ - return 0; -} - /** * sdma_v6_0_load_microcode - load the sDMA ME ucode * @@ -832,7 +806,6 @@ static int sdma_v6_0_start(struct amdgpu_device *adev) r = sdma_v6_0_gfx_resume(adev); if (r) return r; - r = sdma_v6_0_rlc_resume(adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index c55c941b82cf..f3bec3b2d728 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -409,18 +409,6 @@ static void sdma_v7_0_gfx_stop(struct amdgpu_device *adev) } } -/** - * sdma_v7_0_rlc_stop - stop the compute async dma engines - * - * @adev: amdgpu_device pointer - * - * Stop the compute async dma queues. - */ -static void sdma_v7_0_rlc_stop(struct amdgpu_device *adev) -{ - /* XXX todo */ -} - /** * sdma_v7_0_ctx_switch_enable - stop the async dma engines context switch * @@ -448,7 +436,6 @@ static void sdma_v7_0_enable(struct amdgpu_device *adev, bool enable) if (!enable) { sdma_v7_0_gfx_stop(adev); - sdma_v7_0_rlc_stop(adev); } if (amdgpu_sriov_vf(adev)) @@ -643,19 +630,6 @@ static int sdma_v7_0_gfx_resume(struct amdgpu_device *adev) } -/** - * sdma_v7_0_rlc_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * - * Set up the compute DMA queues and enable them. - * Returns 0 for success, error for failure. - */ -static int sdma_v7_0_rlc_resume(struct amdgpu_device *adev) -{ - return 0; -} - static void sdma_v12_0_free_ucode_buffer(struct amdgpu_device *adev) { int i; @@ -878,7 +852,6 @@ static int sdma_v7_0_start(struct amdgpu_device *adev) r = sdma_v7_0_gfx_resume(adev); if (r) return r; - r = sdma_v7_0_rlc_resume(adev); return r; }