ARM: dts: watchdog0 cannot reliably trigger reset

Browse source

On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger
a reset to the CPU. The workaround would be to use watchdog1 instead.

Also for watchdog1, there is a dependency on the bootloader to enable the
boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This
corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the
control register in the clock manager module of Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

...

This commit is contained in:

Dinh Nguyen 2017-01-25 10:01:28 -06:00

parent 7f0f5460d4

commit 59d94d2ed4

1 changed files with 1 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

arch/arm/boot/dts/socfpga_arria10_socdk.dtsi

View file