drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update

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We are preparing for a change where only frontbuffer flush will use
single full frame bit of a new register (SFF_CTL) available on LunarLake
onwards.

It shouldn't be necessary to have SFF bit set if CFF bit is set in
PSR2_MAN_TRK_CTL -> removing setting it on all platforms as there is not
reason to have it different on older platforms.

v2: commit message improved

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250213064804.2077127-2-jouni.hogander@intel.com

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Jouni Högander 2025-02-13 08:47:52 +02:00

parent ac6674bc94

commit 59f38b641a

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drivers/gpu/drm/i915/display/intel_psr.c

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