clk: keystone: add support for post divider register for main pll

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[ Upstream commit 02fdfd708f ]

Main PLL controller has post divider bits in a separate register in
pll controller. Use the value from this register instead of fixed
divider when available.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>

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Murali Karicheri 2015-05-29 12:04:12 -04:00 • committed by Sasha Levin

parent 370f050fc7

commit 5a646e642a

2 changed files with 22 additions and 6 deletions

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8

Documentation/devicetree/bindings/clock/keystone-pll.txt

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20

drivers/clk/keystone/pll.c

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