drm/amd/display: Correct MALL parameters for DCN42 soc bb

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[Why & How]
The MALL and DCC parameters were copied and pasted from a previous ASIC
but the correct value per HW specification should all be 0.

If not correct this can impact urgent bandwidth calculation and PMO.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Nicholas Kazlauskas 2026-03-24 11:50:18 -04:00 • committed by Alex Deucher

parent 5721b5b9c9

commit 5a89553231

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h

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