drm/i915: Move DPLL ref/cri/VGA mode frobbing to the disp2d well enable

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Bunch of stuff needs the DPLL ref/cri clocks on both VLV and CHV,
and having VGA mode enabled causes some problems for CHV. So let's just
pull the code to configure those bits into the disp2d well enable hook.
With the DPLL disable code also fixed to leave those bits alone we
should now have a consistent DPLL state all the time even if the DPLL
is disabled.

This also neatly removes some duplicated code between the VLV and
CHV codepaths.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

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Ville Syrjälä 2015-06-29 15:25:53 +03:00 • committed by Daniel Vetter

parent 4d9194dec3

commit 5a8fbb7d19

1 changed files with 24 additions and 21 deletions

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drivers/gpu/drm/i915/intel_runtime_pm.c

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