drm/amdgpu: Read clock counter via MMIO to reduce delay (v5)

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[Why]
GPU timing counters are read via KIQ under sriov, which will introduce
a delay.

[How]
It could be directly read by MMIO.

v2: Add additional check to prevent carryover issue.
v3: Only check for carryover for once to prevent performance issue.
v4: Add comments of the rough frequency where carryover happens.
v5: Remove mutex and gfxoff ctrl unused with current timing registers.

Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
Acked-by: Horace Chen <horace.chen@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.co>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

YuBiao Wang 2021-06-29 11:21:25 +08:00 • committed by Alex Deucher

parent 51627f0380

commit 5af4438f1e

1 changed files with 14 additions and 7 deletions

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drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

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