clk: qcom: Fix PLL rate configurations

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Sometimes we need to program PLLs with a fixed rate
configuration during driver probe. Doing this after we register
the PLLs with the clock framework causes the common clock
framework to assume the rate of the PLLs are 0. This causes all
sorts of problems for rate recalculations because the common
clock framework caches the rate once at registration time unless
a flag is set to always recalculate the rates.

Split the qcom_cc_probe() function into two pieces, map and
everything else, so that drivers which need to configure some
PLL rates or otherwise twiddle bits in the clock controller can
do so before registering clocks. This allows us to properly
detect the rates of PLLs that are programmed at boot.

Fixes: 49fc825f0c "clk: qcom: Consolidate common probe code"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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This commit is contained in:

Stephen Boyd 2014-07-15 14:59:21 -07:00

parent ff20783f7b

commit 5b6b7490af

3 changed files with 38 additions and 17 deletions

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39

drivers/clk/qcom/common.c

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6

drivers/clk/qcom/common.h

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10

drivers/clk/qcom/mmcc-msm8974.c

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