clk: uniphier: Add SCSSI clock gate for each channel

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[ Upstream commit 1ec09a2ec6 ]

SCSSI has clock gates for each channel in the SoCs newer than Pro4,
so this adds missing clock gates for channel 1, 2 and 3. And more, this
moves MCSSI clock ID after SCSSI.

Fixes: ff388ee365 ("clk: uniphier: add clock frequency support for SPI")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lkml.kernel.org/r/1577410925-22021-1-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Kunihiko Hayashi 2019-12-27 10:42:05 +09:00 • committed by Greg Kroah-Hartman

parent 76cc8bb46b

commit 5b72bb01bc

1 changed files with 8 additions and 5 deletions

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drivers/clk/uniphier/clk-uniphier-peri.c

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