MIPS: bitops: Emit Loongson3 sync workarounds within asm

Browse source

Generate the sync instructions required to workaround Loongson3 LL/SC
errata within inline asm blocks, which feels a little safer than doing
it from C where strictly speaking the compiler would be well within its
rights to insert a memory access between the separate asm statements we
previously had, containing sync & ll instructions respectively.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org

...

This commit is contained in:

Paul Burton 2019-10-01 21:53:35 +00:00

parent c042be02d7

commit 5bb29275df

No known key found for this signature in database

GPG key ID: 3EA79FACB57500DD

1 changed files with 2 additions and 9 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

11

arch/mips/include/asm/bitops.h

View file