drm/amd/display: Ensure DMCUB idle before reset on DCN31/DCN35

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[ Upstream commit c707ea82c7 ]

[Why]
If we soft reset before halt finishes and there are outstanding
memory transactions then the memory interface may produce unexpected
results, such as out of order transactions when the firmware next runs.

These can manifest as random or unexpected load/store violations.

[How]
Increase the timeout before soft reset to ensure the DMCUB has quiesced.
This is effectively 1s maximum based on experimentation.

Use the enable bit check on DCN31 like we're doing on DCN35 and reorder
the reset writes to follow the HW programming guide.

Ensure we're reading SCRATCH7 instead of SCRATCH8 for the HALT code.
No current versions of DMCUB firmware use the SCRATCH8 boot bit to
dynamically switch where the HALT code goes to maintain backwards
compatibility with PSP.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

This commit is contained in:

Nicholas Kazlauskas 2025-02-19 09:56:53 -05:00 • committed by Greg Kroah-Hartman

parent a23f391012

commit 5bf0fd2bd5

2 changed files with 13 additions and 8 deletions

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17

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

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4

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

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