perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking

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Both Auto Counter Reload (ACR) and Architectural PEBS use the PERF_CFG_C
MSRs to configure event behavior. Currently, the driver maintains two
independent variables acr_cfg_c and cfg_c_val to cache the values intended
for these MSRs.

Using separate variables to track a single hardware register state is
error-prone and can lead to configuration conflicts. Consolidate the
tracking into a single cfg_c_val variable to ensure a unified and
consistent view of the PERF_CFG_C MSR state.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260430002558.712334-6-dapeng1.mi@linux.intel.com

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Dapeng Mi 2026-04-30 08:25:58 +08:00 • committed by Peter Zijlstra

parent aa4384bc8f

commit 5c3cdc74af

2 changed files with 8 additions and 9 deletions

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13

arch/x86/events/intel/core.c

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4

arch/x86/events/perf_event.h

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