staging: mt7621-pci: enable clock bit for each port

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The clock related code concerns me from the very beginning because
there are some set ups got from legacy driver that are not documented
anywhere. According to the programming guide 0x7c is 'CPE_ROSC_SEL1'
register and 0x80 is 'CPU_CPE_CN'. I do think this set up is not needed
at all and the proper thing to do is just enable the clock bit for each
pcie port. Hence remove useless code and do the right thing which is
setting up the clock bit for each port enabled.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20200310113459.30539-1-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Sergio Paracuellos 2020-03-10 12:34:59 +01:00 • committed by Greg Kroah-Hartman

parent 05ffb11ca7

commit 5ca61dffc7

1 changed files with 6 additions and 11 deletions

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drivers/staging/mt7621-pci/pci-mt7621.c

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