atl1c: clear bit MASTER_CTRL_CLK_SEL_DIS in atl1c_pcie_patch

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bit MASTER_CTRL_CLK_SEL_DIS could be set before enter suspend
clear it after resume to enable pclk(PCIE clock) switch to
low frequency(25M) in some circumstances to save power.

Signed-off-by: xiong <xiong@qca.qualcomm.com>
Tested-by: Liu David <dwliu@qca.qualcomm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

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Huang, Xiong 2012-04-18 22:01:27 +00:00 • committed by David S. Miller

parent 7f5544d669

commit 5cbdcc2f49

1 changed files with 6 additions and 1 deletions

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7

drivers/net/ethernet/atheros/atl1c/atl1c_main.c

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