ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gate

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The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock,
according to the i.MX6q/sdl reference manuals.  This clock is actually the
gate for several clocks, including the hsi_tx_sel clock's output and the
video_27m clock's output.  The MIPI DSI host controller embedded in the
i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and
MIPI core configuration clock.  In order to gate/ungate the two MIPI DSI
host controller relevant clocks, this patch adds the mipi_core_cfg clock as
a shared clock gate.

Suggested-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

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Liu Ying 2015-02-12 14:01:29 +08:00 • committed by Shawn Guo

parent 721fee59d2

commit 5ccc248cc5

2 changed files with 3 additions and 1 deletions

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arch/arm/mach-imx/clk-imx6q.c

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3

include/dt-bindings/clock/imx6qdl-clock.h

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