clk: thead: Fix TH1520 emmc and shdci clock rate

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[ Upstream commit f4bf0b909a ]

In accordance with LicheePi 4A BSP the clock that comes to emmc/sdhci
is 198Mhz which is got through frequency division of source clock
VIDEO PLL by 4 [1].

But now the AP_SUBSYS driver sets the CLK EMMC SDIO to the same
frequency as the VIDEO PLL, equal to 792 MHz. This causes emmc/sdhci
to work 4 times slower.

Let's fix this issue by adding fixed factor clock that divides
VIDEO PLL by 4 for emmc/sdhci.

Link: 7563179071/drivers/clk/thead/clk-light-fm.c (L454)

Fixes: ae81b69fd2 ("clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks")
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Link: https://lore.kernel.org/r/20241210083029.92620-1-bigunclemax@gmail.com
Tested-by: Xi Ruoyao <xry111@xry111.site>
Reviewed-by: Drew Fustini <dfustini@tenstorrent.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

...

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Maksim Kiselev 2024-12-10 11:30:27 +03:00 • committed by Greg Kroah-Hartman

parent 1c2244437f

commit 5ce6fb470e

1 changed files with 12 additions and 1 deletions

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drivers/clk/thead/clk-th1520-ap.c

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