arm64: kernel: add support for cpu cache information

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This patch adds support for cacheinfo on ARM64.

On ARMv8, the cache hierarchy can be identified through Cache Level ID
(CLIDR) register while the cache geometry is provided by Cache Size ID
(CCSIDR) register.

Since the architecture doesn't provide any way of detecting the cpus
sharing particular cache, device tree is used for the same purpose.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

...

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Sudeep Holla 2015-01-08 10:42:34 +00:00 • committed by Catalin Marinas

parent 26a945caf3

commit 5d425c1865

4 changed files with 152 additions and 19 deletions

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29

arch/arm64/include/asm/cachetype.h

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2

arch/arm64/kernel/Makefile

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128

arch/arm64/kernel/cacheinfo.c

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12

arch/arm64/kernel/cpuinfo.c

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