drm/i915: dvo needs a P2 divisor of 4

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Section 1.5.4, "DPLL A Control Register" from Bspec about bit 23
"FPA0/A1 P2 Clock Divide":

0 = Divide by 2
1 = Divide by 4. This bit must be set in DVO non-gang mode

So copy the current limits (which should be good for i8xx) and create
a new set for dvo encoders.

Reviewed-by: Chris Wilson <chris@chris-wilson.oc.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Daniel Vetter 2013-07-06 12:52:06 +02:00

parent 4a33e48d0e

commit 5d536e2858

1 changed files with 17 additions and 2 deletions

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drivers/gpu/drm/i915/intel_display.c

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