drm/i915: Add chv cmnlane power wells

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CHV has two display PHYs so there are also two cmnlane power wells. Add
the approriate code to power the wells up/down.

Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
enabling at approriate times.

This code actually works on my bsw.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2014-06-28 02:04:08 +03:00 • committed by Daniel Vetter

parent 4811ff4f23

commit 5d6f7ea752

2 changed files with 90 additions and 0 deletions

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drivers/gpu/drm/i915/i915_reg.h

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89

drivers/gpu/drm/i915/intel_pm.c

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