drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating

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HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.

During driver load, init_clock_gating happens after device_info_init_mmio
read the vdbox disable fuse register, so only present vd units will have
these enabled.

BSpec: 14214
HSDES: 1209977827
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Tony Ye <tony.ye@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190823082055.5992-3-lucas.demarchi@intel.com

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This commit is contained in:

Michel Thierry 2019-08-23 01:20:34 -07:00 • committed by Lucas De Marchi

parent b3c0692f36

commit 5d86923060

2 changed files with 21 additions and 1 deletions

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4

drivers/gpu/drm/i915/i915_reg.h

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18

drivers/gpu/drm/i915/intel_pm.c

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