RISC-V: Add defines for the SBI nested acceleration extension

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Add defines for the new SBI nested acceleration extension which was
ratified as part of the SBI v2.0 specification.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241020194734.58686-8-apatel@ventanamicro.com
Signed-off-by: Anup Patel <anup@brainfault.org>

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Anup Patel 2024-10-21 01:17:28 +05:30 • committed by Anup Patel

parent 15ff2ff3c3

commit 5daf89e73d

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arch/riscv/include/asm/sbi.h

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