drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup

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Define the C10 PLL SSC register range via macros, so the HW/SW state of
these register can be verified by a follow-up change, reusing these
macros.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-10-mika.kahola@intel.com

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Imre Deak 2025-11-17 12:45:39 +02:00 • committed by Mika Kahola

parent 230d4c7481

commit 5df82b1792

1 changed files with 8 additions and 2 deletions

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drivers/gpu/drm/i915/display/intel_cx0_phy.c

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