drm/rockchip: dw_hdmi: introduce the VPLL clock setting

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For RK3399 HDMI, there is an external clock need for HDMI PHY,
and it should keep the same clock rate with VOP DCLK.

VPLL have supported the clock for HDMI PHY, but there is no
clock divider bewteen VPLL and HDMI PHY. So we need to set the
VPLL rate manually in HDMI driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>

...

This commit is contained in:

Mark Yao 2017-06-09 15:10:41 +08:00

parent 6445e394c5

commit 5e3bc6d1ab

2 changed files with 25 additions and 2 deletions

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2

Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt

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25

drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c

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