drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start

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While it's not very well understood, there is some sort of a fault
handler implemented in the GMU firmware which triggers when a certain
bit is set, resulting in the M3 core not booting up the way we expect
it to.

Write a magic value to a magic register to hopefully prevent that
from happening.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543335/
Signed-off-by: Rob Clark <robdclark@chromium.org>

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Konrad Dybcio 2023-06-20 13:10:39 +02:00 • committed by Rob Clark

parent 29af760545

commit 5e46ad83db

1 changed files with 6 additions and 0 deletions

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drivers/gpu/drm/msm/adreno/a6xx_gmu.c

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