net: stmmac: fix csr_clk can't be zero issue

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The specific clk_csr value can be zero, and
stmmac_clk is necessary for MDC clock which can be set dynamically.
So, change the condition from plat->clk_csr to plat->stmmac_clk to
fix clk_csr can't be zero issue.

Fixes: cd7201f477 ("stmmac: MDC clock dynamically based on the csr clock input")
Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

...

This commit is contained in:

Biao Huang 2019-05-24 14:26:08 +08:00 • committed by David S. Miller

parent 4523a56115

commit 5e7f7fc538

2 changed files with 7 additions and 4 deletions

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6

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

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5

drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c

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