drm/amdgpu/gfx6: Clean up rings during reset

Browse source

Clear the WPTR and RPTR at ring initialization.
Additionally clear the ring contents too.
This is necessary so that the IP block soft reset can
bring the rings back to a clean state.

After a reset, the ring contents could contain packets
emitted before the reset, and thus need to be cleared
to prevent the command processor from executing packets
left over in the ring from before the reset.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Timur Kristóf 2026-08-03 15:23:04 +02:00 • committed by Alex Deucher

parent c9ddc90f91

commit 5e996008db

1 changed files with 18 additions and 4 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

22

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

View file