drm/msm/a8xx: Add perfcntr flush sequence

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With the slice architecture, we need to flush the slice and unslice
counters to perf RAM before reading counters.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728216/
Message-ID: <20260526145137.160554-13-robin.clark@oss.qualcomm.com>

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Rob Clark 2026-05-26 07:50:46 -07:00

parent 5eedc8c2d0

commit 5ef26a2a4b

3 changed files with 22 additions and 0 deletions

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1

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

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1

drivers/gpu/drm/msm/adreno/a6xx_gpu.h

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20

drivers/gpu/drm/msm/adreno/a8xx_gpu.c

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