arm64: Avoid redundant type conversions in xchg() and cmpxchg()

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Our atomic instructions (either LSE atomics of LDXR/STXR sequences)
natively support byte, half-word, word and double-word memory accesses
so there is no need to mask the data register prior to being stored.

Signed-off-by: Will Deacon <will.deacon@arm.com>

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Will Deacon 2018-09-13 13:30:45 +01:00

parent 3962446922

commit 5ef3fe4cec

3 changed files with 108 additions and 107 deletions

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53

arch/arm64/include/asm/atomic_ll_sc.h

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46

arch/arm64/include/asm/atomic_lse.h

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120

arch/arm64/include/asm/cmpxchg.h

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