ASoC: fsl_sai: Add registers definition for multiple datalines

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SAI IP supports up to 8 data lines. The configuration of
supported number of data lines is decided at SoC integration
time.

This patch adds definitions for all related data TX/RX registers:
	* TDR0..7, Transmit data register
	* TFR0..7, Transmit FIFO register
	* RDR0..7, Receive data register
	* RFR0..7, Receive FIFO register

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20190806151214.6783-2-daniel.baluta@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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Daniel Baluta 2019-08-06 18:12:10 +03:00 • committed by Mark Brown

parent abf31feea2

commit 5f0ac20ed6

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76

sound/soc/fsl/fsl_sai.c

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36

sound/soc/fsl/fsl_sai.h

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